Silicon-on-insulator (SOI) technology is becoming of increasing importance in the field of integrated circuits. SOI technology deals with the formation of transistors in a layer of semiconductor material which overlies an insulating layer. A common embodiment of SOI structures is a single crystal layer of silicon which overlies a layer of silicon dioxide. The invention to be disclosed herein is applicable to all forms of SOI including stacked as well as single layer structures. High performance and high density integrated circuits are achievable using SOI technology because of the reduction of parasitic elements present in integrated circuits formed in bulk semiconductor. For example, for an MOS transistor formed in bulk, parasitic capacitance is present at the junction between the source/drain regions and the underlying substrate, and the possibility of breakdown of the junction between source/drain regions and the substrate regions also exists. A further example of parasitic elements is present for CMOS technology in bulk, where parasitic bipolar transistors formed by n-channel and p-channel transistors in adjacent wells can give rise to latch-up problems. Since SOI structures significantly alleviate parasitic elements, and increase the junction breakdown tolerance of the structure, the SOI technology is well-suited for high performance and high density integrated circuits.
This invention applies to transistors built on all forms of Silicon On Insulator including, for example, heteroepitaxy, such as SOS, beam recrystallization, epitaxial lateral overgrowth, lateral solid phase epitaxy, and single silicon separation (e.g. SIMOX and FIPOS).
The underlying insulator film in an SOI structure presents certain problems relative to the transistor characteristics, however. In bulk transistors, electrical connection is easily made via the substrate to the body node of an MOS transistor. The relatively fixed bias of the body node provides for a stable threshold voltage relative to the drain to source voltage. However, conventional SOI transistors have the body node (i.e., the undepleted volume within the body region underlying the gate electrode) electrically floating, as the body node is isolated from the substrate by the underlying insulator film. Under sufficient drain-to-source bias, impact ionization can generate electron-hole pairs near the drain which, due to the majority carriers traveling to the body node while the minority carriers travel to the drain, cause a voltage differential between the body node and the source of the transistor. This voltage differential lowers the effective threshold voltage and increases the drain current, exhibiting the well known "kink" effect. The "kink" effect is exhibited in the I/V characteristics of transistors by an actual "kink" in the curves.
Furthermore, the structure of the SOI transistor presents a parasitic "back channel" transistor, with the substrate as the gate and the insulator film underlying the transistor as the gate dielectric. This back channel may provide for a drain-source leakage path along the body node near the interface with the insulator film. In addition, the dielectrically isolated body node allows capacitive coupling between the body node and the source and the drain, and diode coupling between the body node and the source and drain, to bias the body node and thus affect the threshold voltage. Each of these factors can contribute to undesirable shifts in the transistor relative to design, as well as to increased instability of the transistor operating characteristics.
It is therefore an object of this invention to provide an insulated-gate field effect transistor formed in semiconductor region overlying an insulator, having reduced resistance from body contact to remote regions of the body.
It is also an object of this invention to provide an insulated-gate field effect transistor formed in semiconductor region overlying an insulator, having a higher back channel Vt while maintaining desired front channel characteristics.